FIG. 1A illustrates a sense amplifier 50 in a state-of-the art dynamic random access memory (DRAM) device comprising a complementary pair of bitlines (BL and BL/) 10 and 12 that intersect with wordlines (WLs) 20 and 22. Only two WLs are shown for simplicity. There is a multiplexer circuit 30 and an equalizer circuit 40 that control the connection and isolation of a sense amplifier 50 with memory array cells at the intersection of the BLs 10 and 12 with WLs 20 and 22. Exemplary memory cells are shown at 60 and 62.
There are also WLs 70 and 72 on the opposite side of the sense amplifier 50 that intersect with BLs 16 and 18. At the intersection there are memory array cells 80 and 82. The sense amplifier 50 is shared by the memory arrays on both sides. There is a multiplexer circuit 90 and equalizer circuit 95 that control the connection and isolation of the sense amplifier 50 with the memory array on the other side. For purposes of this description, the left side memory array is the “t” side and the right side is the “b” side. It should be understood that there is an instance of the circuitry shown in FIG. 1A for each BL pair and in practice there is typically a column of sense amplifiers and their associated multiplexer and equalization circuitry.
The primary purpose of multiplexer circuits 30 and 90 is to isolate the BLs of the unselected memory array during a sense operation (of the selected memory array) and to allow the sense amplifier internal nodes to be precharged via the BL and /BL nodes. The multiplexer is also used to connect the sense amplifier internal nodes to the bitlines of the selected array for reading from and writing to the memory cell. Multiplexer circuit 30 is controlled by multiplexer control signal MUXb and multiplexer circuit 90 is controlled by multiplexer control signal MUXt.
FIG. 1B shows an example of a conventional multiplexer control circuit 100. In practice, there is a multiplexer control circuit that generates the MUXt control signal for controlling the multiplexers on the “t” side of a column of sense amplifiers and a multiplexer control circuit that generates the MUXb control signal for controlling the multiplexers on the “b” side of column of sense amplifiers. The inputs to the multiplexer control circuit 100 are a SELECT signal and an isolation control signal ISOOFF. Generally, the SELECT signal goes high when the memory array on that side (“b” side or “t” side) of the sense amplifier is to be accessed causing the multiplexer control signal to go high, and otherwise is low. The ISOOFF signal goes high when that side of the sense amplifier is to be isolated, causing the multiplexer control signal to go low. The equalization circuits 40 and 95 are controlled by equalization control signals EQLb and EQLt, respectively. The operation is as follows.
In normal operation when a memory array is unselected, the equalizer circuits 40 and 95 are on, precharging BL and /BL and both multiplexer control signals (MUXt and MUXb) are set to a voltage that is high enough to turn on the multiplexer transistors such that the internal sense amplifier nodes (SA and /SA) are brought to the same potential as BL nodes BL and /BL. When a memory cell is selected in an array on one side of the sense amplifier 50 the equalization circuit transistors on that side are turned off while the multiplexer control signal on that side is boosted to a high enough voltage to permit fast reading and writing of data between the internal sense amplifier nodes (SA and /SA) and the BLs (BL and /BL) and the selected array cell. At the same time the multiplexer control signal for the unselected array is turned off to isolate the unselected array for the duration of the memory access while the equalization circuit of the unselected array remains on. The WL to the selected memory cell is then brought to a voltage that is high enough to turn on the cell access transistor and effectively connect the cell capacitor to a bitline (BL or /BL) and after a sufficient time the sense amplifier 50 is turned on to amplify the resulting voltage difference of BL and /BL to a full digital data signal. At the completion of an array access operation the WL is reset back to the unselected potential, the sense amplifier 50 is turned off, and the multiplexer control signals (MUXb and MUXt) and the equalization control signals EQLt and EQLb are returned to the precharging condition.
The multiplexer circuits 30 and 90 devices are normally used to isolate BL nodes from internal sense amplifier nodes during sensing but they can also be used to isolate BL nodes from internal sense amplifier nodes at other times for other purposes. The multiplexer circuits 30 and 90 can be used to isolate BL nodes from internal sense amplifier nodes for reducing bitline leakage due to defects.
Defect leakage current can result from WL-BL short-circuit conditions, thereby consuming more current during standby and self-refresh modes of a memory device. One solution to reduce the impact of WL-BL shorts is the use of a depletion mode n-type field effect transistor (NFET) in the equalization circuits to further limit current sourced into BLs. To fully realize the benefit of a depletion mode NFET current limiter device requires that the shorted BLs be isolated from the sense amplifier nodes by turning off the multiplexers 30 and 90 referred to above.
BL isolation techniques heretofore known only reduce leakage current during self-refresh state of a memory device. In addition, conventional BL isolation techniques involve isolating simultaneously all memory banks with no ability to control the isolation in one bank differently from the isolation in another bank.
Thus, there is room for expanding the benefits of BL isolation in a semiconductor memory device.